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document number: mma26xxnkw rev. 4, 03/2012 freescale semiconductor data sheet: technical data ? 2010-2012 freescale semiconducto r, inc. all ri ghts reserved. dsi inertial sensor the mma26xxnkw family, a safeassure solution, includes dsi2.5 compatible overdamped x-axis satellite accelerometers. features ? 25g to 312.5g nominal full-scale range ? selectable 180 hz, 2-pole, 400 hz, 4-pole, or 800 hz, 4-pole lpf ? dsi2.5 compatible with full support of mandatory commands ? 16 s internal sample rate, with interpolation to 1 ms ? -40c to 125c operatin g temperature range ? pb-free 16-pin qfn, 6 by 6 package ? qualified aecq100, revision g, grade 1 (-40 c to +125 c) ( http://www.aecouncil.com/ ) typical applications ? airbag front and side crash detection for user register array programming, please consult your freescale representative. ordering information device axis range package shipping mma2602nkw x 25g 2086-01 tubes mma2605nkw x 50g 2086-01 tubes mma2606nkw x 62.5g 2086-01 tubes mma2612nkw x 125g 2086-01 tubes mma2618nkw x 187g 2086-01 tubes MMA2631NKW x 312g 2086-01 tubes mma2602nkwr2 x 25g 2086-01 tape & reel mma2605nkwr2 x 50g 2086-01 tape & reel mma2606nkwr2 x 62.5g 2086-01 tape & reel mma2612nkwr2 x 125g 2086-01 tape & reel mma2618nkwr2 x 187g 2086-01 tape & reel MMA2631NKWr2 x 312g 2086-01 tape & reel mma26xxnkw 16-pin qfn case 2086-01 pin connections bottom view top view test2 busrtn test7 v ss test6 test5 busin hcap c rega test4 c reg test3 test1 busout v ssa pcm 1 2 3 4 5 6 7 8 12 11 10 9 16 15 14 13 17
sensors 2 freescale semiconductor, inc. mma26xxnkw application diagram figure 1. application diagram device orientation figure 2. device orientation diagram external component recommendations ref des type description purpose c1 ceramic 100 pf c1 1000 pf 10%, 50v, x7r busin power supply decoupling, esd c3 ceramic, tantalum 1 f c3 100 f, 10%, 50v, x7r reservoir capacitor for keep alive during signaling c4 ceramic 1 f, 10%, 10v, x7r voltage regulator output capacitor (c reg ) c5 ceramic 1 f, 10%, 10v, x7r voltage regulator output capacitor (c rega ) v ss v cc busin busrtn test1 test3 test4 test5 mma26xxn busout busin busrtn test6 hcap v ssa c reg c rega c1 c3 c4 c5 test7 pcm v ss test2 x: 0 g earth ground x: +1 g x: 0 g x: -1 g x: 0 g x: 0 g xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx
sensors freescale semiconductor, inc. 3 mma26xxnkw internal block diagram figure 3. block diagram self-test interface control logic otp array fuse ? converter control in status out oscillator g-cell low-voltage reset serial encoder hcap pcm hcap digital regulator voltage analog regulator voltage c reg c rega v rega v reg v reg v rega v reg reference voltage v ref v ssa test5 test test6 test3 test4 busin v ssb v dsi_ref v dsi_ref busrtn v ss 1z d? ? d1z 1? ? () --------------------------------- 3 sinc filter compensation low-pass filter iir pcm encoder dsp
sensors 4 freescale semiconductor, inc. mma26xxnkw 1 pin connections figure 4. block diagram table 1. pin description pin pin name formal name definition 1 test2 test pin this pin must be left unconnected in the application. 2 test3 test pin this pin must be grounded in the application. 3 test1 test pin this pin must be grounded in the application. 4 busrtn ground this pin is the common return for power and signalling. 5 pcm pcm output this pin provides a 4 mhz pcm signal proportional to the acce leration data for test purposes. the output can be enabled or disabled via otp. if unused, this pin must be left unconnected in the application. reference section 3.5.3.6 . 6 vssb ground this pin must be grounded in the application. 7 busin supply / comm this pin is connected to the dsi positive bus node and provid es the power supply and communication to the system master. an external capacitor must be connected to between this pin and the busrtn pin. reference figure 1 . 8 hcap hold capacitor this pin rectifies the supply voltage on the busin pin to create the supply voltage for the device. an external capacitor must be connected between this pin and the busrtn pin to st ore energy for operation during master communication signalling. reference figure 1 . 9 c reg digital supply this pin is connected to the power supply for the internal digital circuitry. an external capacitor must be connected between this pin and v ss . reference figure 1 . 10 test4 test pin this pin must be grounded in the application. 11 c rega analog supply this pin is connected to the power supply for the internal analog circuitry. an external capacitor must be connected between this pin and v ssa . reference figure 1 . 12 vssa analog gnd this pin is the power supply return node for analog circuitry. 13 test5 test pin this pin enables test mode, and provides the spi programming voltage in test mode. this pin is must be grounded in the application. 14 test6 test pin this pin must be grounded in the application. 15 test7 test pin this pin must be grounded in the application. 16 v ss digital gnd this pin is the power supply return node for the digital circuitry. 17 pad die attach pad this pin is the die attach flag, and should be connected to vss in the application. reference section 5 . corner pads corner pads the corner pads are internally connected to v ss . test2 busrtn test7 v ss test6 test5 busin h cap c rega test4 c reg test3 test1 vssb v ssa pcm 1 2 3 4 5 6 7 8 12 11 10 9 16 15 14 13 17
sensors freescale semiconductor, inc. 5 mma26xxnkw 2 electrical characteristics 2.1 maximum ratings maximum ratings are the extreme limits to which the device ca n be exposed without permanent ly damaging it. do not apply voltages higher than those shown in the table below. 2.2 operating range the operating ratings are the limits normally expected in the application. v l (v cc - v ss ) v h , t l t a t h , t 25 k/min, unless otherwise specified. # rating symbol value unit 1 2 supply voltage (continuous) (busin, hcap) supply voltage (pulsed < 400 ms, repetition rate 60s) (busin, hcap) v cc v cc -0.3 to +30.0 -0.3 to +34.0 v v (3) (3) 3c reg , c rega, pcm, test1, test2, test3, test4, test5, test6, test7 -0.3 to +3.0 v (3) 4 5 busin, busrtn and h cap current maximum duration 1 s continuous i in i in 400 75 ma ma (3) (3) 6 powered shock (six sides, 0.5 ms duration) g pms 2000 g (5) 7 unpowered shock (six sides, 0.5 ms duration) g shock 2000 g (5) 8 drop shock (to concrete, tile or steel surface, 10 drops, any orientation) h drop 1.2 m (5) 9 10 11 electrostatic discharge (per aecq100) hbm (100 pf, 1.5 k ) cdm (r = 0 ) mm (200 pf, 0 ) v esd v esd v esd 2000 500 200 v v v (5) (5) (5) 12 13 temperature range storage junction t stg t j -40 to +125 -40 to +150 c c (3) (3) 14 thermal resistance jc 2.5 c/w (11) # characteristic symbol min typ max units 15 16 supply voltage v hcap busin v hcap v bus v l 6.3 -0.3 ? ? v h 30 30 v v (1,12) (1,12) 17 programming voltage applied to busin (dsi) v pp 14.0 ? 30.0 v (3) 18 programming current busin i pp 85 ?? ma (3) 19 20 operating temperature range t a t a t l -40 -40 ? ? t h +105 +125 c c (1) (3)
sensors 6 freescale semiconductor, inc. mma26xxnkw 2.3 electrical characteristics - supply and i/o v l (v cc - v ss ) v h , t l t a t h , t 25 k/min, unless otherwise specified. 2.4 electrical characteristics - dsi v l (v cc - v ss ) v h , t l t a t h , t 25 k/min, unless otherwise specified # characteristic symbol min typ max units 21 quiescent supply current * i dd ?? 8.0 ma (1) 22 inrush current (excluding hcap capacitor charge current) power on until v reg stable i inrush ?? 20 ma (3) 23 24 internally regulated voltages v reg v rega v reg v rega 2.425 2.425 2.50 2.50 2.575 2.575 v v (1) (1) 25 26 27 v hcap under-voltage detection (see figure 5 ) under-voltage detection threshold v hcap recovery threshold hysteresis (v porhcap_r - v porhcap_f ) v porhcap_f v porhcap_r v hyst_hcap 5.8 ? 70 6.0 ? 100 6.2 6.3 140 v v mv (3,6) (3,6) (3) 28 29 30 31 internal regulator low voltage detection threshold v reg falling v rega falling hysteresis v reg v rega v porvreg_f v porvrega_f v hyst_vreg v hyst_vrega 2.15 2.15 0.05 0.05 2.25 2.25 0.10 0.10 2.40 2.40 0.15 0.15 v v v v (3.6) (3.6) (3) (3) 32 33 external capacitor (c reg , c rega ) capacitance esr (including interconnect resistance) c reg , c rega r cregesr , r cregaesr 500 ? 1000 ? 1500 200 nf m (9) (9) 34 output high voltage (pcm) i load = 100 av oh v reg - 0.1 ?? v(9) 35 output low voltage (pcm) i load = 100 av ol ?? 0.1 v (9) 36 37 temperature monitoring under-temperature monitor threshold over-temperature monitor threshold t under t over ? 155 ? ? -55 ? c c (9) (9) # characteristic symbol min typ max units 38 hcap rectifier leakage current v busin = 0v, v hcap = 9.0v * i rlkg ?? 100 a(1) 39 40 busin to hcap rectifier voltage drop (v busin = 7v) i hcap = -15 ma i hcap = -100 ma * * v rect v rect ? ? 0.75 0.9 1.0 1.2 v v (1) (1) 41 42 busin bias current v busin = 8.0v, v hcap = 9.0v v busin = 4.5v, v hcap = 24v, no response current *i busin_bias i busin_bias -100 -100 ? ? 100 100 a a (1) (1) 43 busin response current v busin = 4.0v * i resp 9.9 11 12.1 ma (1) 44 45 busin logic thresholds signal threshold frame threshold * * v ths v thf 2.8 5.5 3.0 6.0 3.2 6.5 v v (1) (1) 46 47 busin logic hysteresis signal frame * * v hyss v hysf 30 100 ? ? 90 300 mv mv (3) (3)
sensors freescale semiconductor, inc. 7 mma26xxnkw 2.5 electrical characte ristics - signal chain v l (v cc - v ss ) v h , t l t a t h , t 25 k/min, unless otherwise specified. # characteristic symbol min typ max units 48 49 50 51 52 53 54 55 sensitivity (10-bit @ 100 hz referenced to 0 hz) 25g range 50g range 62.5g range 125g range 187g range 312g range total sensitivity error (including non-linearity) t a = 25 c t l t a t h * * * * * * * * sens sens sens sens sens sens sens_25 sens ? ? ? ? ? ? -5 -7 20.48 10.24 8.192 4.096 2.731 1.638 ? ? ? ? ? ? ? ? +5 +7 lsb/g lsb/g lsb/g lsb/g lsb/g lsb/g % % (1,14) (1,14) (1,14) (1,14) (1,14) (1,14) (1) (1) 56 digital offset 10-bit output * off 10bit 460 512 564 lsb (1) 57 58 range of output (10-bit mode) acceleration internal error range acc range err 1 ? ? 0 1023 ? lsb lsb (3) (3) 59 60 cross-axis sensitivity z-axis to x-axis y-axis to x-axis v zx v yx -5 -5 ? ? +5 +5 % % (3) (3) 61 adc output noise peak (1 hz - 1 khz, 10-bit) n sd -4 ? +4 lsb (3) 62 system output noise (10-bit, rms, all ranges) n rms ?? +1.2 lsb (3) 63 64 non-linearity (all ranges) 10-bit output, range < 50g 10-bit output, 50g range 312.5g nl out_sub50g nl out_sub250g -2 -2 ? ? +2 +2 % % (3) (3)
sensors 8 freescale semiconductor, inc. mma26xxnkw 2.6 electrical characteristics - self-test and overload v l (v cc - v ss ) v h , t l t a t h , t 25 k/min, unless otherwise specified. # characteristic symbol min typ max units 65 acceleration (without hitting internal g-cell stops) 25g, 50g, 62.5g, 125g g g-cell_clip60x 400 456 500 g (9) 66 acceleration (without hitting internal g-cell stops) 187g, 312g g g-cell_clip240x 1750 2065 2300 g (9) 67 ? and sinc filter clipping limit 25g g adc_clip60x 98 108 121 g (9) 68 ? and sinc filter clipping limit 50g g adc_clip60x 191 210 232 g (9) 69 ? and sinc filter clipping limit 62.5g g adc_clip60x 191 210 232 g (9) 70 ? and sinc filter clipping limit 125g g adc_clip120x 353 379 409 g (9) 71 ? and sinc filter clipping limit 187g g adc_clip240x 1690 1876 2106 g (9) 72 ? and sinc filter clipping limit 312g g adc_clip480x 1690 1876 2106 g (9) 73 74 75 76 77 78 deflection, 10-bit, self-test - offset, 30 sample ave, t a = 25 c) 25g range 50g range 62.5g range 125g range 187g range 312g range * * * * * * dflct_x25 dflct_x50 dflct_x62 dflct_x125 dflct_x187 dflct_x312 ? ? ? ? ? ? 246 123 98 49 82 49 ? ? ? ? ? ? lsb lsb lsb lsb lsb lsb (1) (1) (1) (1) (1) (1)) 79 self-test deflection range, t a = 25 c dflct -10 ? +10 % (1) 80 self-test deflection range, t l t a t h dflct -20 ? +20 % (1)
sensors freescale semiconductor, inc. 9 mma26xxnkw 2.7 dynamic electrical characteristics - dsi v l (v cc - v ss ) v h , t l t a t h , t 25 k/min, unless otherwise specified. # characteristic symbol min typ max units 81 82 83 84 reset recovery (see figure 20 ) por negated to 1st dsi command (initialization command) por negated to acceleration data valid (including lpf init) dsi clear command to 1st dsi command (initialization command) dsi clear command to acceleration data valid (including lpf init) t dsi_init t dsp_init t dsi_init t dsp_init ? ? ? ? 400 / f osc ? 400 / f osc ? ? 10000 / f osc ? 10000 / f osc s s s s (7) (7) (7) (7) 85 hcap under-voltage reset delay (see figure 5 ) v hcap < v porhcap_f to por assertion t hcap_por ? 880 / f osc ? s(7) 86 v reg under-voltage reset delay (see figure 6 ) v reg < v porvreg_f to por assertion t vreg_por ?? 5 s(3) 87 v rega under-voltage reset delay (see figure 7 ) v rega < v porvrega_f to por assertion t vrega_por ?? 5 s(3) 88 89 90 v reg , v rega capacitor monitor por to first capacitor test disconnect disconnect time () disconnect rate () t por_captest t captest_time t captest_rate ? ? ? 12000 / f osc 6 / f osc 256 / f osc ? ? ? s s s (7) (7) (7) 91 communication data rate d rate 100 ? 200 kbps (7) 92 loss of signal reset time maximum time below frame threshold t to 2.00 ? 4.00 ms (7) 93 busin response current slew rate 1.0 ma to 9.0 ma, 9.0 to 1.0 ma t itr 0.33 ? 10.0 ma/ s(3) 94 95 busin timing to response current busin negative voltage transition =3.0v to i rsp = 7.0 ma rise busin negative voltage transition =3.0v to i rsp = 5.0 ma fall t rsp_r t rsp_f ? ? ? ? 2.50 2.50 s s (7) (7) 96 97 dsi busin signal duty cycle logic ?0? logic ?1? * * d cl d ch 10 60 33 67 40 90 % % (7) (7) 98 99 100 inter-frame separation time (see figure 8 ) following read write nvm command following initialization following other dsi bus commands t ifs t ifs t ifs 2 20 20 ? ? ? ? ? ? ms s s (7) (7) (7) 101 dsi data latency t lat_dsi 4 / f osc ? 5 / f osc s(7) 102 otp program timing time to program one otp bit t prog_bit 64 ? 256 s(7) 103 104 105 106 107 108 self-test response time self-test activation time (eof slave to 90% dflct_xxx, 180 hz lpf) self-test deactivation time (eof slave to 10% dflct_xxx, 180 hz lpf) self-test activation time (eof slave to 90% dflct_xxx, 400 hz lpf) self-test deactivation time (eof slave to 10% dflct_xxx, 400 hz lpf) self-test activation time (eof slave to 90% dflct_xxx, 800 hz lpf) self-test deactivation time (eof slave to 10% dflct_xxx, 800 hz lpf) t st_act_180 t st_deact_180 t st_act_400 t st_deact_400 t st_act_800 t st_deact_800 2.00 2.00 1.00 1.00 0.50 0.50 ? ? ? ? ? ? 5.00 5.00 2.50 2.50 1.75 1.75 ms ms ms ms ms ms (7) (7) (7) (7) (7) (7) 109 error detection response time mirror register crc error to status flag (s) set (factory or user array) t crc_err ? 75 / f osc ? s(7)
sensors 10 freescale semiconductor, inc. mma26xxnkw 2.8 dynamic electrical char acteristics - signal chain v l (v cc - v ss ) v h , t l t a t h , t 25 k/min, unless otherwise specified. notes: 1. parameters tested 100% at final test at -40 c, 25 c, and 105 c. 2. parameters tested 100% at probe. 3. verified by characterization. 4. * indicates critical characteristic. 5. verified by qualification testi ng, not tested in production. 6. parameters verified by pass/fail testing in production. 7. functionality guaranteed by modeling, si mulation and/or design verification. circui t integrity assured through iddq and scan testing. timing is determined by internal system clock frequency. 8. verified by user system level characterization, not tested in production, or at component level. 9. verified by simulation. 10.measured at final test. self-test activation occurs under control of the test program. 11.thermal resistance between the die junction and the ex posed pad; cold plate is attached to the exposed pad. 12.maximum voltage characterized. minimum voltage tested 100% at final test. maximum voltage tested 100% to 24v at final test. 13.n/a. 14.sensitivity, and overload capabili ty specifications will be r educed when 80hz filter is selected. 15.filter cutoff frequencies are directly d ependent upon the internal oscillator frequency. 16.target values. actual values to be determined during device characterization. # characteristic symbol min typ max units 110 internal oscillator frequency * f osc 3.80 4 4.20 mhz (1) 111 data interpolation latency t lat_interp 64 / f osc ? 65 / f osc s(7) 112 113 114 115 116 117 dsp low-pass filter cutoff frequency lpf0 (referenced to 0 hz) filter order lpf0 cutoff frequency lpf1 (referenced to 0 hz) filter order lpf1 cutoff frequency lpf2 (referenced to 0 hz) filter order lpf2 f c_lpf0 o lpf0 f c_lpf1 o lpf1 f c_lpf2 o lpf2 171 ? 380 ? 760 ? 180 2 400 4 800 4 189 ? 420 ? 840 ? hz 1 hz 1 hz 1 (7) (7) (7) (7) (7) (7) 118 119 sensing element rolloff frequency (-3 db) 25g, 50g, 62.5g, 125g 187g, 312g f gcell_3db_xlo f gcell_3db_xhi 938 3952 ? ? 2592 14370 hz hz (9) (9) 120 121 sensing element natural frequency 25g, 50g, 62.5g, 125g 187g, 312g f gcell_xlo f gcell_xhii 12651 26000 ? ? 13871 28700 hz hz (9) (9) 122 123 sensing element damping ratio 25g, 50g, 62.5g, 125g 187g, 312g gcell_xlo gcell_xhi 2.760 1.260 ? ? 6.770 3.602 ? ? (9) (9) 124 125 sensing element delay (@100 hz) 25g, 50g, 62.5g, 125g 187g, 312g f gcell_delay100_xlo f gcell_delay100_xhi 63 13 ? ? 170 40 s s (9) (9) 126 package resonance frequency f package 100 ?? khz (9)
sensors freescale semiconductor, inc. 11 mma26xxnkw figure 5. v hcap under-voltage detection figure 6. v reg under-voltage detection figure 7. v rega under-voltage detection v porhcap_r v hcap v porhcap_f v hyst_hcap t hcap_por uv uv: under-voltage condition exists uv por v porvreg_r v reg v porvreg_f v hyst_vreg por t vreg_por v porvrega_r v rega v porvrega_f v hyst_vrega por t vrega_por
sensors 12 freescale semiconductor, inc. mma26xxnkw figure 8. dsi bus inter-frame timing t ifs_slave t ifs_master logic ?1? logic ?0? t start_master t start_slave busin? i response 1ma 9ma t rsp_r t itr t itr t rsp_f v ths v thf dsp_out t lat_dsi t lat_interp eof slave
sensors freescale semiconductor, inc. 13 mma26xxnkw 3 functional description 3.1 user accessible data array a user accessible data array allows for each device to be cu stomized. the array consists of an otp factory programmable array, an otp user programmable array, and read only regist ers for device status. the otp a rrays incorporate independent crc circuitry for fault detection (reference section 3.2 ). portions of the factory programm able array are reserved for factory-pro- grammed trim values. the user accessi ble data is shown in the table below. type codes f: freescale programmed otp locationu/f:user and/or freescale programmed otp location. r: read-only registeru:user programmed otp location. note: unused and unprogrammed spare bits always read ?0?. 3.1.1 device serial number registers a unique serial number is programmed into the serial number re gisters of each device during manufacturing. the serial num- ber is composed of the following information: serial numbers begin at 1 for all produced devices in each lo t, and are sequentially assigned. lot numbers begin at 1 and are sequentially assigned. no lot will contain more devices than ca n be uniquely identified by the 13-bit serial number. depending on lot size and quantities, all possible lot numbers and serial numbers may not be assigned. the serial number registers are included in the factory programmed otp crc verification. reference section 3.2.1 for details regarding the crc verification. beyond this, the contents of the seri al number registers have no impact on device operation or performance, and are only used for traceability purposes. table 2. user accessible data byte addr ra[3:0] register nibble addr wa[3:0] bit function nibble addr (wa[3:0]) bit function type 7 6 5 4 3 2 1 0 $00 sn0 sn[7] sn[6] sn[5] sn[4] sn[3] sn[2] sn[1] sn[0] f $01 sn1 sn[15] sn[14] sn[13] sn[12] sn[11] sn[10] sn[9] sn[8] $02 sn2 sn[23] sn[22] sn[21] sn[20] sn[19] sn[18] sn[17] sn[16] $03 sn3 sn[31] sn[30] sn[29] sn[28] sn[27] sn[26] sn[25] sn[24] $04 type reference table 39 lpf[1] lpf[0] 1 0 reference table 39 rng[3] rng[2] rng[1] rng[0] u/f $05 devcfg devid unused unused unused unus ed crc_u[2] crc_u[1] crc_u[0] $06 devcfg1 ud00[5] ud00[4] ud00[3] ud00[2] ud00[1] ud00[0] at_otp[1] at_otp[0] $07 devcfg2 lock_u unused pcm reserved addr[3] addr[2] addr[1] addr[0] $08 ud01 ud01[7] ud01[6] ud01[5] ud01[4] ud01[3] ud01[2] ud01[1] ud01[0] $09 ud02 ud02[7] ud02[6] ud02[5] ud02[4] ud02[3] ud02[2] ud02[1] ud02[0] $0a ud03 ud03[7] ud03[6] ud03[5] ud03[4] ud03[3] ud03[2] ud03[1] ud03[0] $0b ud04 ud04[7] ud04[6] ud04[5] ud04[4] ud04[3] ud04[2] ud04[1] ud04[0] $0c ud05 ud05[7] ud05[6] ud05[5] ud05[4] ud05[3] ud05[2] ud05[1] ud05[0] $0d ud06 ud06[7] ud06[6] ud06[5] ud06[4] ud06[3] ud06[2] ud06[1] ud06[0] $0e ud07 ud07[7] ud07[6] ud07[5] ud07[4] ud07[3] ud07[2] ud07[1] ud07[0] $0f ud08 ud08[7] ud08[6] ud08[5] ud08[4] ud08[3] ud08[2] ud08[1] ud08[0] bit range content sn[12:0] serial number sn[31:13] lot number
sensors 14 freescale semiconductor, inc. mma26xxnkw 3.1.2 device type register (type) the device type register is an otp configuration register whic h contains device configuration information. bit 5 - bit 0 are factory programmed and are included in the factory programmed ot p crc verification. these bits are read only to the user. bit 7 - bit 6 are user programmable otp bits and are included in the user programmable otp crc verification. 3.1.2.1 low-pass filter select ion bits (lpf[1:0]) (type[7:6]) the low-pass filter selection bit selects between one of three lo w-pass filter options. these bits can be factory or user pro- grammed. this filter option is not implemented. lpf[1:0] must not be set to this value to guarantee proper operation and performance. 3.1.2.2 range selection bits (rng[3:0]) (type[3:0]) the range selection bits indicate the full-scale range of the device, as shown below. these bits are factory programmed. table 3. factory configuration register location bit ra[3:0] register wa[3:0] 7 6 5 4 wa[3:0] 3 2 1 0 $04 type bnk0 $08 lpf[1] lpf[0] 1 0 rng[3] rng[2] rng[1] rng[0] factory default 0010 0000 lpf[1] lpf[0] low-pass filter selected 0 0 400 hz, 4-pole 0 1 not enabled 1 1 0 180 hz, 2-pole 1 1 800 hz, 4-pole rng[3] rng[2] rng[1] rng[0] full-scale range g-cell design 0000 n / a n / a 0001 2 5 g m e d i u m - g 0010 5 0 g m e d i u m - g 0011 6 2 g m e d i u m - g 0100 1 2 5 g m e d i u m - g 0101 1 8 7 g h i g h - g 0110 3 1 2 g h i g h - g 0111 n / a n / a 1000 reserved n/a 1001 1010 1011 1100 1101 1110 1111
sensors freescale semiconductor, inc. 15 mma26xxnkw 3.1.3 device configuration register (devcfg) the device configuration register is a user programmable otp register which co ntains device configuration information. this register is included in the user register crc check. refer to section 3.2.2 for details regarding the crc for the user programma- ble otp array. 3.1.3.1 device id bit (devcfg[7]) the device id bit is a user programmable bit which allows the user to select between 2 device ids. the device id is trans- mitted in response to the request id dsi command. reference section 4.2.1.5 for more information regarding the request id dsi command. this bit can be factory or user programmed. 3.1.3.2 user configuration crc (crc_u[2:0], devcfg[2:0]) the user configuration crc bits contain the 3-bit crc used for verification of the user programmable otp array. reference section 3.2.2 for details regarding the crc for the user programmable ot p array. these bits can be factory or user programmed. 3.1.4 device configuration register 1 (devcfg1) the device configuration register is a user programmable otp register which co ntains device configuration information. this register is included in the user register crc check. refer to section 3.2.2 for details. 3.1.4.1 user specific data 00 bits (ud00[5:0], devcfg1[7:2]) the user specific data bits have no impact on the device function or performance. the bits can be programmed with user or assembly specific information. these bi ts can be factory or user programmed. 3.1.4.2 attribute bits (at_otp[1:0], devcfg1[1:0]) the attribute bits are user defined bits which are transmitted in response to the request status, disable self-test stimulus or enable self-test stimulus dsi commands. the transmitted values are qualified by the lock_u bit as shown in the table below. these bits can be factory or user programmed. table 4. device control register location bit ra[3:0] register wa[3:0] 7 6 5 4 wa[3:0] 3 2 1 0 $05 devcfg bnk0 $0a1000 bnk0 $09 0 crc_u[2] crc_u[1] crc_u[0] factory default 1000 0000 devid device id 0 ?00110? 1 ?00100? table 5. device control register 1 location bit ra[3:0] register wa[3:0] 7 6 5 4 wa[3:0] 3 2 1 0 $06 devcfg1 bnk2 $06 ud00[5] ud00[4] ud00[3] ud00[2] bnk1 $06 ud00[1] ud00[0] at_otp[1] at_otp[0] factory default 0000 0000 lock_u devcfg1 values dsi transmitted values at_otp[1] at_otp[0] at[1] at[0] 0xx10 1 0000 0101 1010 1111
sensors 16 freescale semiconductor, inc. mma26xxnkw 3.1.5 device configuration 2 register (devcfg2) device configuration register 2 is a user programmable otp register which contains device configuration information. this register is included in the user register crc check. refer to section 3.2.2 for details regarding the crc for the user programma- ble otp array. 3.1.5.1 user configuration loc k bit (lock_u, devcfg2[7]) the lock_u bit is a factory or user programmed otp bit which inhibits writes to the user configuration array when active. reference section 3.2.2 for details regarding the lock_u bit and crc verification. 3.1.5.2 pcm bit (devcfg2[5]) the pcm bit enables the pcm output pin. when the pcm bit is set, the pcm output pin is active and outputs a pulse code modulated signal proportional to the acceleration response. reference section 3.5.3.6 for more information regarding the pcm output. when the pcm output is cl eared, the pcm output pin is actively pulled lo w. this bit can be factory or user programmed. 3.1.5.3 device address (addr[3:0], devcfg2[3:0]) the device address bits define the preprogrammed dsi bus devi ce address. if the device addr ess bits are programmed to ?0000?, there is not preprogrammed address, and the address must be assigned via the initialization dsi command. reference section 4.2.1.1 for more details regarding the initialization dsi co mmand. these bits can be factory or user programmed. 3.1.6 user data registers (udx) the user data registers are user programmable otp register which can be programmed with user or assembly specific in- formation. these registers have no impact on the device performanc e, but are included in the user register crc check. refer to section 3.2.2 for details regarding the user register crc check. these registers can be factory or user programmed. table 6. device control register location bit ra[3:0] register wa[3:0] 7 6 5 4 wa[3:0] 3 2 1 0 $07 devcfg2 bnk0 $07 bnk2 $07 bnk3 $07 bnk3 $0f lock_u unused pcm reserved bnk1 $07 addr[3] addr[2] addr[1] addr[0] factory default 0000 0000 location bit ra[3:0] register wa[3:0] 7 6 5 4 wa[3:0] 3 2 1 0 $08 ud01 bnk2 $08 ud01[7] ud01[6] ud01[5] ud01[4] bnk1 $08 ud01[3] ud01[2] ud01[1] ud01[0] $09 ud02 bnk2 $09 ud02[7] ud02[6] ud02[5] ud02[4] bnk1 $09 ud02[3] ud02[2] ud02[1] ud02[0] $0a ud03 bnk2 $0a ud03[7] ud03[6] ud03[5] ud03[4] bnk1 $0a ud03[3] ud03[2] ud03[1] ud03[0] $0b ud04 bnk2 $0b ud04[7] ud04[6] ud04[5] ud04[4] bnk1 $0b ud04[3] ud04[2] ud04[1] ud04[0] $0c ud05 bnk2 $0c ud05[7] ud05[6] ud05[5] ud05[4] bnk1 $0c ud05[3] ud05[2] ud05[1] ud05[0] $0d ud06 bnk2 $0d ud06[7] ud06[6] ud06[5] ud06[4] bnk1 $0d ud06[3] ud06[2] ud06[1] ud06[0] $0e ud07 bnk2 $0e ud07[7] ud07[6] ud07[5] ud07[4] bnk1 $0e ud07[3] ud07[2] ud07[1] ud07[0] $0f ud08 bnk2 $0f ud08[7] ud08[6] ud08[5] ud08[4] bnk1 $0f ud08[3] ud08[2] ud08[1] ud08[0] factory default 0000 0000
sensors freescale semiconductor, inc. 17 mma26xxnkw 3.2 otp array lock and crc verification 3.2.1 factory programmed otp array lock and crc verification the factory programmed otp array is verified for errors with a 3-bit crc. the crc verification is enabled only when the factory programmed otp array is locked and the lock is active. t he lock is active only after an automatic otp readout in which the internal lock bit is read as ?1?. automatic otp readouts occur only after por or a dsi clear command is received. the factory programmed otp array is locked by freescale and will always be active after por. the crc is continuously calculated on the factory programmed otp arra y, which includes the registers listed below: bits are fed in from right to left (lsb first), and top to bo ttom (lower addresses first) in the register map. the crc verifica tion uses a generator polynomial of g(x) = x 3 + x +1, with a seed value = ?111?. the calculated crc is compared against the crc_f[2:0] bits. if a crc mismatch is detected, an internal dat a error is set and the device responds to dsi messages as spec- ified in section 4.3 . the crc verification is completed on the memory registers which hold a copy of the fuse array values, not the fuse array values. 3.2.2 user programmable otp array lock and crc verification the user programmable otp array is inde pendently verified for errors with a 3-bit crc. the crc verification is enabled only when the user programmable otp array is locked and the lock is active. the lock is active only after an automatic otp readout in which the lock_u bit is read as ?1?. automatic otp rea douts occur only after por or a dsi clear command is received. once the lock_u bit is active, the crc is continuously calc ulated on the user programmable otp array, which includes the registers listed below: bits are fed in from right to left (lsb first), and top to bo ttom (lower addresses first) in the register map. the crc verifica tion uses a generator polynomial of g(x) = x 3 + x+ 1, with a seed value = ?111?. the ca lculated crc is compared against the user programmed crc, crc_u[2:0], which is also included in the user programmable array. if a crc mismatch is detected, an in- ternal data error is set, and the device responds to dsi messages as specified in section 4.3 . the crc verification is completed on the memory registers which hold a copy of the fuse array valu es, not the fuse array values. writes to the user programmable otp array using the write nvm command will update the mirror regist ers and result in a change to the crc calculation regard- less of the state of the lock_u bit. a crc mismatch will only be detected if the lock_u bit is active. factory lock bit value in fuse array lock bit value in mirror register after automatic readout lock bit active? crc verification enabled? 0 n/a no no 1 0n o n o 1 1 yes yes register name register addresses included in factory crc? serial number registers sn0, sn1, sn2, sn3 yes type register type[5:0] yes factory programmable device configuration bits internal register map yes factory otp array crc crc_f[2:0] no factory otp array lock bit lock_f no factory lock bit value in fuse array lock bit value in mirror register after automatic readout lock bit active? crc verification enabled? 0 n/a no no 1 0n o n o 1 1 yes yes register name register addresses included in user crc? type register type[7:6] yes device id bit devcfg[7]: 1 yes user data register 0 devcfg1[7:2]: ud00[5:0] yes attribute bits devcfg1[1:0]: at_otp[1:0] yes pcm bit devcfg2[5]: pcm yes reserved bit devcfg2[4] yes device address devcfg2 [3:0]: addr[3:0] yes user data registers 1 - 8 ud01 - ud08 yes user programmable otp array crc devcfg[2:0]: crc_u[2:0] no user programmable otp array lock bit devcfg2[7]: lock_u no
sensors 18 freescale semiconductor, inc. mma26xxnkw 3.3 voltage regulators the device derives its internal supply voltage from the hcap supply voltage. the device includes separate internal voltage regulators for the analog (v rega ) and digital circuitry (v reg ). external filter capacitors are required, as shown in figure 1 . the voltage regulator module includes voltage monitoring circuitry which holds the device in reset following power-on until the hcap and internal voltages have stabilized sufficiently for pro per operation. the voltage monitor asserts internal reset when t he hcap supply or internally regulated voltages fall below predetermined levels. a reference generator provides a stable voltage which is used by the ? converter. figure 9. voltage regulation and monitoring 3.3.1 c reg and c rega regulator capacitor the internal regulator requires an external capacitor between the c reg pin and v ss pin, and the c rega pin and v ssa pin for stability. figure 1 shows the recommended types and values for each of these capacitors. 3.3.2 v hcap voltage monitor the device includes a circuit to monitor the voltage on the hcap pin. if the voltage falls below the specified threshold in section 2 , the device will be reset within the reset delay time (t hcap_por ) specified in section 2.7 . c rega c reg hcap voltage regulator reference generator v rega = 2.50 v digital logic dsp otp array oscillator ? converter bias generator trim trim v ref_mod = 1.250 v v reg = 2.50 v bandgap reference v buf v ref v rega por v ref comparator comparator hcap comparator v rega v reg voltage regulator analog filter delay t vreg_por analog filter delay t vreg_por digital delay t hcap_por voltage regulator v buf
sensors freescale semiconductor, inc. 19 mma26xxnkw 3.3.3 v reg , and v rega under-voltage monitor the device includes a circuit to moni tor the internally regulated voltages (v reg and v rega ). if either of the internal regulator voltages fall below the specified thresholds in section 2 , the device will be reset within the reset delay time (t vreg_por , t vrega_por ) specified in section 2.7 . 3.3.4 v reg and v rega capacitance monitor a monitor circuit is incorporated to ensure predicta ble operation if the connection to the external c reg or c rega capacitor becomes open. at a continuous rate specified in section 2.7 (t captest_rate ), both regulators are simultaneously disabled for a short duration (t captest_time ). if either of the external capacitors are not pr esent, the associated regulator voltage will fall below the internal reset threshol d, forcing a device reset. figure 10. v reg capacitor monitor figure 11. v rega capacitor monitor 3.4 internal oscillator the device includes a factory trimmed oscillator as specified in section 2.8. cap_test v reg time capacitor present v porvreg_f por capacitor open t captest_time t captest_rate cap_test v rega time capacitor present v porrega_f por capacitor open t captest_time t captest_rate
sensors 20 freescale semiconductor, inc. mma26xxnkw 3.5 acceleration signal path 3.5.1 transducer the device transducer is an overda mped mass-spring-damper system descri bed by the followin g transfer function: where: = damping ratio n = natural frequency = 2 ?? f n reference section 2.8 for transducer parameters. 3.5.2 ? converter the sigma delta converter provides the interface betw een the g-cell and the dsp block. the output of the ? converter is a data stream at a nominal frequency of 1 mhz. figure 12. ? converter block diagram 3.5.3 digital signal processing block a digital signal processing (dsp) block is used to perform si gnal filtering and compensation op erations. a diagram illustrating the signal processing flow within the dsp block is shown in figure 13 . figure 13. signal chain diagram hs () ?? ? 1-bit quantizer z -1 1 - z -1 z -1 1 - z -1 first integrator second integrator 1 = 1 2 2 v x c int1 g-cell c bot c top c = c top - c bot ? _out v = 2 v ref adc dac v = c x v x / c int1 ? _out sinc filter 1z d? ? d1z 1? ? () 0 ? () ? () ? () ? () ? () ? () ? () ? () ?? low-pass filter output output compensation a b e c d f interpolation scaling
sensors freescale semiconductor, inc. 21 mma26xxnkw 3.5.3.1 decimation sinc filter the serial data stream produced by the ? converters is decimated and converted to parallel values by a 3rd order 16:1 sinc filter with a decimation factor of 16. figure 14. sinc filter response, t s = 16 s table 7. signal chain characteristics description sample time ( s) data width (bits) over range (bits signal width (bits) signal noise (bits) signal margin (bits) typical block latency reference a ? 1 1 1 112/f osc section 3.5.2 b sinc filter 16 20 12 4 section 3.5.3.1 c low-pass filter 16 26 1 12 4 9 reference section 3.5.3.2 section 3.5.3.2 d compensation 16 26 4 10 3 9 24/f osc section 3.5.3.3 e dsp sampling 16 10 4/f osc section 3.5.3.5 10-bit output scaling f interpolation 1 10 64/f osc section 3.5.3.5 hz () 1z 16? ? 16 1 z 1? ? () ------------------- --------------- - 3 =
sensors 22 freescale semiconductor, inc. mma26xxnkw 3.5.3.2 low-pass filter data from the sinc filter is processed by an infinite impulse response (iir) low-pass filter. the device provides the option for one of three low-pass filters. t he filter is selected with the lpf[1:0] bits in the type reg ister. the filter selection options are listed in section 3.1.2.1 , table 8 . response parameters for the lo w-pass filter are specified in sec- tion 2.8 . filter characteristics are i llustrated in the figures below. note: low-pass filter figures do not include g-cell frequency response. table 8. low-pass filter coefficients description filter coefficients group delay 180 hz lpf a 0 0.000534069200512 4608/f osc n 11 0.25 d 11 1 n 12 0.499999985098839 d 12 -1.959839582443237 n 13 0.25 d 13 0.960373640060425 n 21 1d 21 1 n 22 0d 22 0 n 23 0d 23 0 400 hz lpf a 0 0.003135988372378 3392/f osc n 11 0.000999420881271 d 11 1.0 n 12 0.001998946070671 d 12 -1.892452478408814 n 13 0.000999405980110 d 13 0.89558845758438 n 21 0.250004753470421 d 21 1.0 n 22 0.499986037611961 d 22 -1.919075012207031 n 23 0.250009194016457 d 23 0.923072755336761 800 hz lpf a 0 0.011904109735042 1728/f osc n 11 0.003841564059258 d 11 1.0 n 12 0.007683292031288 d 12 -1.790004611015320 n 13 0.003841534256935 d 13 0.801908731460571 n 21 0.250001862645149 d 21 1.0 n 22 0.499994158744812 d 22 -1.836849451065064 n 23 0.250003993511200 d 23 0.852215826511383 hz () a 0 n 11 z 0 ? () n 12 z 1? ? () n 13 z 2? ? () ++ d 11 z 0 ? () d 12 z 1? ? () d 13 z 2? ? () ++ -------------------------------------------------------------------------------------------- n 21 z 0 ? () n 22 z 1? ? () n 23 z 2? ? () ++ d 11 z 0 ? () d 22 z 1? ? () d 23 z 2? ? () ++ -------------------------------------------------------------------------------------------- ?? =
sensors freescale semiconductor, inc. 23 mma26xxnkw figure 15. low-pass filter characteristics: f c = 180 hz, 2-pole, t s = 16 s
sensors 24 freescale semiconductor, inc. mma26xxnkw figure 16. low-pass filter characteristics: f c = 400 hz, 4-pole, t s = 16 s
sensors freescale semiconductor, inc. 25 mma26xxnkw figure 17. low-pass filter characteristics: f c = 800 hz, 4-pole, t s = 16 s
sensors 26 freescale semiconductor, inc. mma26xxnkw 3.5.3.3 compensation the device includes internal compensation circuitry to compensate for sensor offset, sensitivity and non-linearity. 3.5.3.4 data interpolation the device includes 16 to 1 linear data interpolation to minimize the system sample jitter. each result produced by the digital signal processing chain is delayed one sample time. on reception of an acceleration data request, the transmitted data is inter - polated from the 2 previous samples, resulting in a latency of one sample time, and a maximum signal jitter of 1/16 of a sampl e time. reference figure 8 for more information regardin g interpolation and data latency. 3.5.3.5 output scaling the 26 bit digital output from the dsp is clipped and scaled to a 10-bit or 8-bit word which covers the acceleration range of the device. figure 18 shows the method used to establish the accele ration data word from the 26-bit dsp output. figure 18. output scaling diagram 3.5.3.6 pcm output function the device provides the option for a pcm output function. the pc m output is activated if the pcm bit is set in the devcfg2 register. when the pcm function is enabled, a 4 mhz pulse code modulated signal proportional to the upper 9 bits of the accel- eration response is output onto the pcm pin. the pcm output is intended for test us e only. a block diagram of the pcm output is shown in figure 19 . figure 19. pcm output function block diagram over range signal noise margin d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 ... d2 d1 d0 10 bit data word d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 using truncation 9 bit data word d21 d20 d19 d18 d17 d16 d15 d14 d13 using truncation 8 bit data word d21 d20 d19 d18 d17 d16 d15 d14 using truncation output scaling d_x[9:1] a 9 bit adder pcm b carry sum f clk = 4 mhz sample updated every 16 s 9 9 9 d ff clk q q d ff clk q q d ff clk q q d ff clk q q d ff clk q q d ff clk q q d ff clk q q d ff clk q q d ff clk q q
sensors freescale semiconductor, inc. 27 mma26xxnkw 3.6 device initialization following powerup, under-voltage reset or reception of a dsi clear command, the device proceeds through an initialization process as described in the following tables: figure 20. initialization timing table 9. powerup or under-voltag e reset initialization process # description time s flag st flag dsi response 1 power up to a known state 0 n/a n/a no response 3 read fuse array and copy to memory array (mirror registers) 1 0 no response 4 initialize dsi state machine (the device is ready for dsi messages) t dsi_init 10 dsi read acceleration data short response = zero. dsi read acceleration data long response = invalid data. 5 initialize the dsp (acceleration data is valid) t dsp_init 0 0 normal table 10. dsi clear command initialization process # description time s flag st flag dsi response 1 the device logic comes out of reset 0 1 0 no response 3 read fuse array and copy to memory array (mirror registers) 1 0 no response 4 initialize dsi state machine (the device is ready for dsi messages) t dsi_init 10 dsi read acceleration data short response = zero. dsi read acceleration data long response = invalid data. 5 initialize the dsp (acceleration data is valid) t dsp_init 0 0 normal t int_init busin? dsp_out v porhcap_r v hcap dsi ready por v reg v rega v porvreg_r v porvrega_r internal delay t dsp_init t dsi_init
sensors 28 freescale semiconductor, inc. mma26xxnkw 3.7 overload response 3.7.1 overload performance the device is designed to operate within a specified range. ho wever, acceleration beyond that range (overload) impacts the operating range output of the sensor. acce leration beyond the range of the device can generate a dc shift at the output of the device that is dependent upon the overload frequency and amp litude. the device g-cell is over damped, providing the optimal design for overload performance. however, the performance of the device during an overload condition is affected by many other parameters, including: ? g-cell damping ? non-linearity ? clipping limits ? symmetry figure 21 shows the g-cell, sigma delta, and output clipping of t he device over frequency. the relevant parameters are spec- ified in section 2 . figure 21. output clipping vs. frequency 3.7.2 sigma delta overrange response overrange conditions exist when the signal level is beyond the full-scale range of the device bu t within the computational limi ts of the dsp. the ? converter can saturate at le vels above those specified in section 2 (g adc_clip ). the dsp operates predict- ably under all cases of overrange, although the signal may inclu de residual high frequency components for some time after re- turning to the normal range of operation due to non-linear effects of the sensor. 5khz f g-cell f lpf g adc_clip g g-cell_clip determined by g-cell 10khz g-cell rolloff acceleration (g) frequency (khz) lpf rolloff r e g i o n c l i p p e d b y g - c e l l r e g i o n c l i p p e d b y a d c r e g i o n o f s i g n a l d i s t o r t i o n d u e t o a s y m m e t r y a n d n o n - l i n e a r i t y region of no signal distortion beyond specification region of interest roll-off and adc clipping g range_norm determined by g-cell roll-off and full-scale range region clipped by output
sensors freescale semiconductor, inc. 29 mma26xxnkw 4 dsi protocol layer 4.1 communication interface overview the device is compatible with the dsi bus standard v2.5. 4.1.1 dsi physical layer reference dsi bus standard v2.5, section 3 for information regarding the physical layer. 4.1.2 dsi data link layer reference dsi bus standard,v2.5, section 4 for information r egarding the dsi data link layer. the sections below describe the dsi data link layer features supported. 4.2 dsi protocol 4.2.1 dsi bus commands dsi bus commands ar e summarized in table 11 . the device supports only the command formats specified in section 4.2.1 . the device will ignore commands of any other format. if a crc error is detected, or a reserved or un-implemented command is received, the device will not respond. following all messages, the device requires a minimum inter-frame separation (t ifs ). as long as the mi nimum inter-frame sep- aration times defined in section 4.2.1 are met, all supported commands are guaran teed to be executed, and the device will be ready for the next message. the device will respond as appropriate during the subsequ ent dsi transfer. exactly one response is attempted. table 11. dsi bus command summary command command format data c3 c2 c1 c0 hex description d7 d6 d5 d4 d3 d2 d1 d0 0000 $0initialization standard long only nv bsbnk[1]bnk[0]pa[3]pa[2]pa[1]pa[0] 0001 $1request status standard/enhanced l/s ???????? 0010 $2read acceleration datastandard/enhanced l/s ???????? 0011 $3not implemented not implemented not implemented 0100 $4request id informationstandard/enhanced l/s ???????? 0101 $5not implemented not implemented not implemented 0110 $6not implemented not implemented not implemented 0111 $7clear standard/enhanced l/s ???????? 1000 $8not implemented not implemented not implemented 1001 $9read write nvm standard/enhanced lwa[3]wa[2]wa[1]wa[0]rd[3]rd[2]rd[1]rd[0] 1010$aformat control standard/enhanced lr/wfa[2]fa[1]fa[0]fd[3]fd[2]fd[1]fd[0] 1011$bread register data standard/enhanced l 0 0 0 0 ra[3]ra[2]ra[1]ra[0] 1100$cdisable self-test standard/enhanced l/s ???????? 1101$dactivate self-test standard/enhanced l/s ???????? 1110$enot implemented not implemented not implemented 1111$freverse initialization not implemented not implemented
sensors 30 freescale semiconductor, inc. mma26xxnkw 4.2.1.1 initialization command the initialization command conforms to the description provided in sect ion 6.1.1 of the dsi bus standard v2.5. the initializa- tion command is only supported as a standard long command. no other commands are recognized by the device until a valid standard long initialization command is received. if the bs bit is set in the initialization co mmand, the device will be reset within t bsopen. if the device has been preprogrammed, pa[3:0] and a[3:0] must match the preprogrammed address. if no device address has been previously programmed into the ot p array, pa[3:0] contains the device address, and a[3:0] must be zero. if either addressing condition is not met, the device address is not assigned, and the device will not respond to the initialization command. if the addressing co nditions are met, the new device address is assigned to a[3:0]. once the device ad- dress is assigned, the new address (a[3:0]) is not protected by the user programmable otp a rray crc verification. the user programmable otp array crc is calculated and verified using the otp programmed va lues of a[3:0] = ?0000?. once initialized, the device will no longer recognize or respond to initialization commands. table 12. initialization command data address command crc d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] a[3] a[2] a[1] a[0] c[3] c[2] c[1] c[0] nv bs bnk[1]bnk[0]pa[3]pa[2]pa[1]pa[0]a[3]a[2]a[1]a[0]00004 bits table 13. initialization command bit definitions bit field definition c[3:0] initialization command = ?0000? a[3:0] dsi device address. this address is set to the preprogrammed device address following reset, or to ?0000? if no preprogrammed a ddress has been assigned. pa[3:0] dsi address to be programmed. bnk[1:0] these bits select the bank address for the user writable data registers. bank selection affects the read/write nvm command oper ation. invalid combinations of b1 and b0 result in no response fr om the device to the associated initialization. refer to section 4.2.1.10 for fur- ther details regarding register programming and bank selection. bs no bus switch is included in the device: 1 - the device is reset. 0 - normal operation nv nvm program enable. this bit enables programming of the user-programmed otp locations. data to be programmed is transferred to the device during subsequent read write nvm commands. 1 - enable otp programming 0 - disable otp programming table 14. initialization command response response crc d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] pa[3] pa[2] pa[1] pa[0] 0 0 0 bf nv 0 bnk[1] bnk[0] pa[3] pa[2] pa[1] pa[0] 4 bits table 15. initialization response bit definitions bit field definition pa[3:0] dsi device address. this field contains the device address. if the device is unprogrammed when the initialization command is is sued, the device address is assigned. this field contai ns the programmed address. an initialization command which attempts to assign a de vice address of zero is ignored. bnk[1:0] these bits select the bank address for the user writable data registers. bank selection affects the read/write nvm command oper ation. invalid combinations of b1 and b0 result in no response fr om the device to the associated initialization. refer to section 4.2.1.10 for fur- ther details regarding register programming and bank selection. nv nvm program enable. this bit indicates if programming of the user-accessible otp is enabled. 1 - otp programming enabled 0 - otp programming disabled bf this bit indicates the success or failure of the bus test performed as part of the initialization command. 1 - bus fault detected 0 - bus test passed
sensors freescale semiconductor, inc. 31 mma26xxnkw 4.2.1.2 request status command the request status command is supported in the following command formats: ? standard long command ? standard short command ? enhanced long command as configured by the format control command (reference section 4.2.1.11 ) ? enhanced short command as configured by the format control command (reference section 4.2.1.11 ) the device ignores the request status command if the dsi device address is set to the dsi global device address of ?0000?. the data bits d[7:0] in the command are only used in the crc calculation. table 16. request status command data address command crc d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] a[3] a[2] a[1] a[0] c[3] c[2] c[1] c[0] ? ? ? ? ? ? ? ? a[3]a[2]a[1]a[0]00010 to 8 bits table 17. request status command bit definitions bit field definition c[3:0] request status command = ?0001? a[3:0] dsi device address. this field contains the device address. th is field must match the internal programmed address field. otherw ise, the command is ignored. d[7:0] used for crc calculation only table 18. short response - request status command response crc d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0 0 0 0 0 0 0nvust 0 at[1] at[0] s 0 0 to 8 bits table 19. long response - request status command data crc d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] a[3]a[2]a[1]a[0]0000nvust 0 at[1] at[0] s 0 0 to 8 bits table 20. request status response bit definitions bit field definition s this bit indicates whether the device has detected an internal device error. 1 - internal error detected. 0 - no internal error detected reference ta b l e 5 9 for conditions that set the s bit. at[1:0] attribute bits located in register devcfg1 (reference section 3.1.4.2 ) st this bit indicates whether internal self-test circuitry is active 1 - self-test active 0 - self-test disabled u this bit is set if the voltage at hcap is below the threshold specified in section 2 . refer to section 3.3.2 for details. nv nvm program enable. this bit indicates whether programmi ng of the user-programmable otp locations is enabled. 1 - otp programming enabled 0 - otp programming disabled a[3:0] dsi device address. this field contains the device address. shaded bits are transmitted to meet the response message length of the received message
sensors 32 freescale semiconductor, inc. mma26xxnkw 4.2.1.3 read acceleration data command the read acceleration data command is supported in the following command formats: ? standard long command ? standard short command ? enhanced long command as configured by the format control command (reference section 4.2.1.11 ) ? enhanced short command as configured by the form at control command (reference section 4.2.1.11 ) the device ignores the request status command if the dsi devic e address is set to the dsi global device address of ?0000?. the data bits d[7:0] in the command are only used in the crc calculation. the device truncates the lsbs for acceleration data responses of length less than 10. if the result of the truncation is 0, the minimum acceleration value is transmitted as defined in table 26 . table 21. read acceleration data command data address command crc d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] a[3] a[2] a[1] a[0] c[3] c[2] c[1] c[0] ? ? ? ? ? ? ? ? a[3]a[2]a[1]a[0]00100 to 8 bits table 22. read acceleration data command bi t definitions bit field definition c[3:0] read acceleration data command = ?0010? a[3:0] dsi device address. this field contains the device address. this field must match the internal programmed address field. otherw ise, the command is ignored. d[7:0] used for crc calculation only table 23. short response - read acceleration data command response length response crc d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 8 ad[9] ad[8] ad[7] ad[6] ad[5] ad[4] ad[3] ad[2] 0 to 8 bits 9 ad[9] ad[8] ad[7] ad[6] ad[5] ad[4] ad[3] ad[2] ad[1] 10 ad[9] ad[8] ad[7] ad[6] ad[5] ad[4] ad[3] ad[2] ad[1] ad[0] 11 s 12 0 13 st 14 at_otp[0] 15 at_otp[1] table 24. long response - read acceleration data command response crc d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] a[3] a[2] a[1] a[0] 0 s ad[9] ad[8] ad[7] ad[6] ad[5] ad[4] ad[3] ad[2] ad[1] ad[0] 0 to 8 bits table 25. read acceleration response bi t definitions bit field definition ad[9:0] 10-bit acceleration result produced by the device. s this bit indicates whether the device has detected an internal device error. 1 - internal error detected. 0 - no internal error detected reference table 59 for conditions that set the s bit. st this bit indicates whether inter nal self-test circuitry is active 1 - self-test active 0 - self-test disabled a[3:0] dsi device address. this field contains the device address. at_otp[1:0] attribute bits located in register devcfg1 (reference section 3.1.4.2 ) shaded bits are transmitted to meet the res ponse message length of the received message
sensors freescale semiconductor, inc. 33 mma26xxnkw 4.2.1.4 dsi command #3 dsi command ?0011? is not implemented. the device ignor es all command formats with a command id of ?0011?. table 26. acceleration data values 8-bit data value 9-bit data value 10-bit data value description decimal hex decimal hex decimal hex 255 0xff 511 0x1ff 1023 0x3ff maximum positive acceleration value ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? positive acceleration values 131 0x83 259 0x103 515 0x203 130 0x82 258 0x102 514 0x202 129 0x81 257 0x101 513 0x201 128 0x80 256 0x100 512 0x200 typical 0 g level 127 0x7f 127 0x0ff 511 0x1ff negative acceleration values 126 0x7e 126 0x0fe 510 0x1fe 125 0x7d 125 0x0fd 509 0x1fd ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 111111m a x i m u m n e g a t i v e a c c e l e r a t i o n v a l u e 000000s e n s o r e r r o r
sensors 34 freescale semiconductor, inc. mma26xxnkw 4.2.1.5 request id information command the request id information command is supported in the following command formats: ? standard long command ? standard short command ? enhanced long command as configured by the format control command (reference section 4.2.1.11 ) ? enhanced short command as configured by the format control command (reference section 4.2.1.11 ) the device ignores the request id information command if the dsi device address is set to the dsi global device address of ?0000?. the data bits d[7:0] in the co mmand are only used in the crc calculation. 4.2.1.6 dsi command #5 dsi command ?0101? is not implemented. the device ignores all command formats with a command id of ?0101?. 4.2.1.7 dsi command #6 dsi command ?0110? is not implemented. the device ignor es all command formats with a command id of ?0110?. table 27. request id information command data address command crc d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] a[3] a[2] a[1] a[0] c[3] c[2] c[1] c[0] ? ? ? ? ? ? ? ? a[3]a[2]a[1]a[0]01000 to 8 bits table 28. request id informati on command bit definitions bit field definition c[3:0] request id information data command = ?0100? a[3:0] dsi device address. this field contains the device address. this field must match the internal programmed address field. otherw ise, the command is ignored. d[7:0] used for crc calculation only table 29. short response - re quest id information command response crc d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0 0 0 0 0 0 0v2v1v0011100 to 8 bits table 30. long response - request id information command response crc d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] a[3]a[2]a[1]a[0]0000v[2]v[1]v[0]0devid1000 to 8 bits table 31. request id response bit definitions bit field definition d[4:0] = {1?b0,devid, 3?b100} device identifier:?00100?, or ?01100? devid: bit 7 of the devcfg register v[2:0] version id. this field indicates t he device / silicon revision of the device. a[3:0] dsi device address. this field contains the device address. shaded bits are transmitted to meet the res ponse message length of the received message
sensors freescale semiconductor, inc. 35 mma26xxnkw 4.2.1.8 clear command the clear command is supported in the following command formats: ? standard long command ? standard short command ? enhanced long command as configured by the format control command (reference section 4.2.1.11 ) ? enhanced short command as configured by the format control command (reference section 4.2.1.11 ) when the device successfully decodes a clear command, and th e address field matches either the assigned device address (pa[3:0]) or the dsi global address of ?0000? the device logic is reset. reference section 3.6 for the initialization sequence fol- lowing a clear command. the data bits d[7:0] in the command are only used in the crc calculation. there is no response to the clear command. 4.2.1.9 dsi command #8 dsi command ?1000? is not implemented. the device ignores all command formats with a command id of ?1000?. table 32. clear command data address command crc d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] a[3] a[2] a[1] a[0] c[3] c[2] c[1] c[0] ? ? ? ? ? ? ? ? a[3]a[2]a[1]a[0]01110 to 8 bits table 33. clear comma nd bit definitions bit field definition c[3:0] clear command = ?0111?. when a clear command is successfully decoded and the address field matches either the assigned device address or the dsi global device address of ?0000? the device logic is reset. reference section 3.6 for the initialization sequence following a clear command. a[3:0] dsi device address. this field contains the device address. this field must match the internal programmed address field or the global device address of ?0000?. otherwise, the command is ignored. d[7:0] used for crc calculation only
sensors 36 freescale semiconductor, inc. mma26xxnkw 4.2.1.10 write nvm command the write nvm command is supported in the following command formats: ? standard long command ? enhanced long command as configured by the format control command (reference section 4.2.1.11 ) the device ignores the write nvm command if the command is in any other format, or if the dsi device address is set to the dsi global device address of ?0000?. the write nvm command uses the nibble address definitions in ta b l e 2 and summarized in table 39 . writes to otp occur only if the nv bit is set. the nv bit is set by the initialization command (reference section 4.2.1.1 ). if the nv bit is cleared when the command is executed, the mirror registers addressed by wa[3:0] are updated with the contents of rd[3:0] and the dsi device address is returned regardless of the wa[3:0] value. if the write nvm command is a request to change the device address, the new device address is returned. the dsi bus idle voltage must exceed the minimum v pp voltage when programming the otp array. no internal verification of the vpp voltage is completed while writing is in process. to ve rify proper writes, it is recomm end that the registers be read b ack after writes to verify proper contents. the tota l execution time for the write nvm command is t prog_bit times the number of bits being programmed (1 - 4 bits). inter-frame spacing between the write nvm command and the subsequent dsi command must accommodate this timing. writes to the user programmable otp array using the write nvm command will update the mirror registers and result in a change to the crc calculation regardless of the state of the nv bit and the lock_u bit. a crc mismatch will only be detected if the lock_u bit is active (reference section 3.2.2 ). table 34. write nvm command data address command crc d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] a[3] a[2] a[1] a[0] c[3] c[2] c[1] c[0] wa[3]wa[2]wa[1]wa[0]rd[3]rd[2]rd[1]rd[0]a[3]a[2]a[1]a[0]10010 to 8 bits table 35. write nvm command bit definitions bit field definition c[3:0] write nvm command = ?1001? a[3:0] dsi device address. this field contains the device address. this field must match the internal programmed address field. otherw ise, the command is ignored. rd[3:0] rd[3:0] contains the data to be written to the ot p location addressed by wa[3:0] when the nv bit is set. wa[3:0] wa[3:0] contains the nibble address of the otp register to be written to when the nv bit is set. table 36. long response - write nvm command (nv = 1) data crc d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] a[3] a[2] a[1] a[0] wa[3] wa[2] wa[1] wa[0] 1 1 bnk[1] bnk[0] rd[3] rd[2] rd[1] rd[0] 0 to 8 bits table 37. long response - write nvm command (nv = 0) data crc d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] a[3]a[2]a[1]a[0]00001111a[3]a[2]a[1]a[0]0 to 8 bits table 38. write nvm response bit definitions bit field definition bnk[1:0] these bits provide the bank address selected in the initialization command. a[3:0] dsi device address. this field contains the device address. this field must match the internal programmed address field. otherw ise, the command is ignored. rd[3:0] rd[3:0] contains the contents of the registers a ddressed by wa[3:0] after the execution of the nvm write. wa[3:0] wa[3:0] contains the nibble address of the otp register to be written to when the nv bit is set.
sensors freescale semiconductor, inc. 37 mma26xxnkw table 39. otp register nibble address assignments bank address register address (nibble) register description bnk[1] bnk[0] wa[3] wa[2] wa[1] wa[0] x x0000 unused no write to nvm executed, normal res ponse: rd[3:0] = devi ce address addr[3:0] x x0001 unused no write to nvm executed, normal re sponse: rd[3:0] = devi ce address addr[3:0] x x0010 x x0011 x x0100 x x0101 0 00110 unused no write to nvm executed, normal res ponse: rd[3:0] = devi ce address addr[3:0] 0 00111 devcfg2[7] only rd[3] is written to the lock_u bit 0 01000 type[7:6] only rd[3:2] is written to lpf[1:0] 0 01001 devcfg[3:0] rd[3] is written to devcfg[3] - unused, rd[2:0] is written to crc_u[2:0] 0 01010 devcfg[7:4] rd[3:0] is written to devcfg[7:4] - unused 0 01011 unused no write to nvm executed, normal res ponse: rd[3:0] = devi ce address addr[3:0] 0 01100 unused no write to nvm executed, normal res ponse: rd[3:0] = devi ce address addr[3:0] 0 01101 unused no write to nvm executed, normal res ponse: rd[3:0] = devi ce address addr[3:0] 0 01110 unused no write to nvm executed, normal res ponse: rd[3:0] = devi ce address addr[3:0] 0 01111 unused no write to nvm executed, normal res ponse: rd[3:0] = devi ce address addr[3:0] 0 10110 devcfg1[3:0] rd[3:2] is written to ud00[1:0], rd[1:0] is written to at[1:0] 0 10111 devcfg2[3:0] rd[3:0] is written to addr[3:0] 0 11000 ud01[3:0] rd[3:0] is written to ud01[3:0] 0 11001 ud02[3:0] rd[3:0] is written to ud02[3:0] 0 11010 ud03[3:0] rd[3:0] is written to ud03[3:0] 0 11011 ud04[3:0] rd[3:0] is written to ud04[3:0] 0 11100 ud05[3:0] rd[3:0] is written to ud05[3:0] 0 11101 ud06[3:0] rd[3:0] is written to ud06[3:0] 0 11110 ud07[3:0] rd[3:0] is written to ud07[3:0] 0 11111 ud08[3:0] rd[3:0] is written to ud08[3:0] 1 00110 devcfg1[7:4] rd[3:0] is written to ud00[5:2] 1 00111 devcfg2[5] only rd[1] is written to the pcm bit 1 01000 ud01[7:4] rd[3:0] is written to ud01[7:4] 1 01001 ud02[7:4] rd[3:0] is written to ud02[7:4] 1 01010 ud03[7:4] rd[3:0] is written to ud03[7:4] 1 01011 ud04[7:4] rd[3:0] is written to ud04[7:4] 1 01100 ud05[7:4] rd[3:0] is written to ud05[7:4] 1 01101 ud06[7:4] rd[3:0] is written to ud06[7:4] 1 01110 ud07[7:4] rd[3:0] is written to ud07[7:4] 1 01111 ud08[7:4] rd[3:0] is written to ud08[7:4] 1 10110 unused no write to nvm executed, normal res ponse: rd[3:0] = devi ce address addr[3:0] 1 10111 devcfg2[6] only rd[2] is written to the devcfg2[6] bit (unused) 1 11000 unused no write to nvm executed, normal res ponse: rd[3:0] = devi ce address addr[3:0] 1 11001 unused no write to nvm executed, normal res ponse: rd[3:0] = devi ce address addr[3:0] 1 11010 unused no write to nvm executed, normal res ponse: rd[3:0] = devi ce address addr[3:0] 1 11011 unused no write to nvm executed, normal res ponse: rd[3:0] = devi ce address addr[3:0] 1 11100 unused no write to nvm executed, normal res ponse: rd[3:0] = devi ce address addr[3:0] 1 11101 unused no write to nvm executed, normal res ponse: rd[3:0] = devi ce address addr[3:0] 1 11110 unused no write to nvm executed, normal res ponse: rd[3:0] = devi ce address addr[3:0] 1 11111 devcfg2[4] only rd[0] is written to devcfg2[4]
sensors 38 freescale semiconductor, inc. mma26xxnkw 4.2.1.11 format control command the format control command is supported in the following command formats: ? standard long command ? enhanced long command as configured by the format control command (reference section 4.2.1.11 ) the device ignores the format control command if the command is in any other format. the device supports the format con- trol command with the dsi global address of ?0000?, but does not provide a response. the format control registers defined in the dsi bus standard v2.5 are shown in table 44 . the reset values assigned to each register are also indicated. table 40. format control command data address command crc d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] a[3] a[2] a[1] a[0] c[3] c[2] c[1] c[0] r/wfa[2]fa[1]fa[0]fd[3]fd[2]fd[1]fd[0]a[3]a[2]a[1]a[0]10100 to 8 bits table 41. format control command bit definitions bit field definition c[3:0] format control command = ?1010? a[3:0] dsi device address. this field contains the device address. this field must match the internal programmed address field. otherw ise, the command is ignored. fd[3:0] data to be written to the format control register addressed by fa[2:0] if the r/w bit is set to ?1?. fa[2:0] the address of the format control register to read or written. r/w read/write determines if the register at address fa[2:0] is to be read or written. 1 - write fd[3:0] to the format control register addressed by fa[2:0] 0 - read the format control register addressed by fa[2:0] table 42. long response - format control command response crc d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] a[3]a[2]a[1]a[0]0110r/wfa[2]fa[1]fa[0]fd[3]fd[2]fd[1]fd[0]0 to 8 bits table 43. format control response bit definitions bit field definition fd[3:0] the contents of the format control register addressed by fa[2:0]. fa[2:0] the address of the format control register that was read or written. r/w read/write indicates if the register at address fa[2:0] was read or written. 1 - fd[3:0] contains the data written to the format control register addressed by fa[2:0] 0 - fd[3:0] contains the contents for the format control register addressed by fa[2:0] a[3:0] dsi device address. this field contains the device address. table 44. format control register values format control register register address reset values dsi standard values definition fa[2] fa[1] fa[0] fd[3] fd[2] fd[1] fd[0] fd[3] fd[2] fd[1] fd[0] crc polynomial - low nibble 00000010001 crc polynomial = x 4 + 1 crc polynomial - high nibble 00100010001 seed - low nibble 01010101010 seed = ?1010? seed - high nibble 01100000000 crc length (0 to 8) 10001000100 crc length = 4 short word data length (8 to 15)10110001000short comm and length = 8 reserved 11000000000 n/a format selection 11100000000 n/a
sensors freescale semiconductor, inc. 39 mma26xxnkw the following restrictions apply to format control register operations: ? writes to the crc length register of values greater than 8 are ignored. the cont ents of the register are unchanged. ? writes to the short word data length register of values less than 8 are ignored. the contents of the register are unchanged. the contents of the format selection regist er determine whether the standard dsi val ues or the values in the format control registers are used. if the format selection register contains ?1111?, the format contro l register values are active. any write to the format control registers will become active upon completion of the write. in this case, the response to a format control com- mand will maintain the format of the previous command resulting in an invalid response. a write of ?0000? to the format selection register activates the standard dsi values. a write to the format selection register of any other value is ignored. 4.2.1.12 read register data command the read register data command is supported in the following command formats: ? standard long command ? enhanced long command as configured by the format control command (reference section 4.2.1.11 ) the device ignores the register data command if the command is in any other format, or if the dsi device address is set to the dsi global device address of ?0000?. the read register command uses the byte address definitions shown in table 2 . readable registers along with their byte ad- dresses are shown in ta b l e 2 . table 45. read register data command data address command crc d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] a[3] a[2] a[1] a[0] c[3] c[2] c[1] c[0] 0000ra[3]ra[2]ra[1]ra[0]a[3]a[2]a[1]a[0]10110 to 8 bits table 46. read register da ta command bit definitions bit field definition c[3:0] read register data command = ?1011? a[3:0] dsi device address. this field contains the device address. this field must match the internal programmed address field. otherw ise, the command is ignored. ra[3:0] ra[3:0] contains the byte address of the register to be read. table 47. long response - read register data command data crc d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] a[3] a[2] a[1] a[0] ra[3] ra[2] ra[1] ra[0] rd[7] rd[6] rd[5] rd[4] rd[3] rd[2] rd[1] rd[0] 0 to 8 bits table 48. read register data response bit definitions bit field definition rd7:0] rd[7:0] contains the data of the register addressed by ra[3:0]. ra[3:0] ra[3:0] contains the byte address of the register to be read. a[3:0] dsi device address. this field contains the device address. this field must match the internal programmed address field. otherw ise, the command is ignored.
sensors 40 freescale semiconductor, inc. mma26xxnkw 4.2.1.13 disable self-test command the disable self-test command is supported in the following command formats: ? standard long command ? standard short command ? enhanced long command as configured by the format control command (reference section 4.2.1.11 ) ? enhanced short command as configured by the format control command (reference section 4.2.1.11 ) the data bits d[7:0] in the command are only used in the crc ca lculation. the device supports the disable self-test command with the dsi global address of ?0000?, but does not provide a response. the disable self-test command removes the voltage from the self-t est plate of the transducer whic h results in the acceleration output value returning to the 0g offset value within t st_deact_xxx , as specified in section 2 . a self-test lockout is activated when the device receives two consecutive disable self-test co mmands once self-test lockout is activated, the internal self-test circuitry is disabled until one of the following conditions occurs: ? hcap under-voltage ? a clear command is received ? internal regulator under-vo ltage resulting in a reset ? a frame timeout resulting in a reset table 49. disable self-test command data address command crc d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] a[3] a[2] a[1] a[0] c[3] c[2] c[1] c[0] ? ? ? ? ? ? ? ? a[3]a[2]a[1]a[0]11000 to 8 bits table 50. disable self-test command bit definitions bit field definition c[3:0] disable self-test command = ?1100? a[3:0] dsi device address. this field contains the device address. this field must match the internal programmed address field. otherw ise, the command is ignored. d[7:0] used for crc calculation only table 51. short response - disable self-t est command response crc d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0 0 0 0 0 0 0nvust 0 at[1] at[0] s 0 0 to 8 bits table 52. long response - disable self-test command data crc d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] a[3]a[2]a[1]a[0]0000nvust 0 at[1] at[0] s 0 0 to 8 bits table 53. disable self-test response bit definitions bit field definition s this bit indicates whether the device has detected an internal device error. 1 - internal error detected. 0 - no internal error detected reference table 59 for conditions that set the s bit. at[1:0] attribute bits located in register devcfg1 (reference section 3.1.4.2 ) st this bit indicates whether inter nal self-test circuitry is active 1 - self-test active 0 - self-test disabled u this bit is set if the voltage at hcap is below the threshold specified in section 2 . refer to section 3.3.2 for details. nv nvm program enable. this bit indicates whether programmi ng of the user-programmable otp locations is enabled. 1 - otp programming enabled 0 - otp programming disabled a[3:0] dsi device address. this field contains the device address.
sensors freescale semiconductor, inc. 41 mma26xxnkw 4.2.1.14 enable self-test command the enable self-test command is supported in the following command formats: ? standard long command ? standard short command ? enhanced long command as configured by the format control command (reference section 4.2.1.11 ) ? enhanced short command as configured by the format control command (reference section 4.2.1.11 ) the data bits d[7:0] in the command are only used in the cr c calculation. the device ignores the enable self-test command when it is sent to the dsi global address of ?0000?. the enable self-test command applies a voltage to the self-test plate of the transducer which results in a delta in the accel- eration output value of dflct _xxx within t st_act_xxx , as specified in section 2 . this remains present until the disable self-test command is received. activation of the self-test circuit is in hibited if the self-test locking has been ac tivated. if self-test locking is activated , the internal self-test circuitry remains disabled, a nd the st bit is cleared in the response. self-test locking is described in section 4.2.1.13 . table 54. enable self-test command data address command crc d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] a[3] a[2] a[1] a[0] c[3] c[2] c[1] c[0] ? ? ? ? ? ? ? ? a[3]a[2]a[1]a[0]11014 bits table 55. enable self-test command bit definitions bit field definition c[3:0] enable self-test command = ?1101? a[3:0] dsi device address. this field contains the device address. this field must match the internal programmed address field. otherw ise, the command is ignored. d[7:0] used for crc calculation only table 56. short response - enable self-test command response crc d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 0 0 0 0 0 0 0nvust 0 at[1] at[0] s 0 4 bits table 57. long response - enable self-test command data crc d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] a[3]a[2]a[1]a[0]0000nvust 0 at[1] at[0] s 0 4 bits table 58. enable self-test response bit definitions bit field definition s this bit indicates whether the device has detected an internal device error. 1 - internal error detected. 0 - no internal error detected reference table 59 for conditions that set the s bit. at[1:0] attribute bits located in register devcfg1 (reference section 3.1.4.2 ) st this bit indicates whether inter nal self-test circuitry is active 1 - self-test active 0 - self-test disabled u this bit is set if the voltage at hcap is below the threshold specified in section 2 . refer to section 3.3.2 for details. nv nvm program enable. this bit indicates whether programmi ng of the user-programmable otp locations is enabled. 1 - otp programming enabled 0 - otp programming disabled a[3:0] dsi device address. this field contains the device address.
sensors 42 freescale semiconductor, inc. mma26xxnkw 4.2.1.15 dsi command #14 dsi command ?1110? is not implemented. the device ignores all command formats with a command id of ?1110?. 4.2.1.16 reverse initialization command the reverse initialization command is not implemented. the device ignores all command fo rmats with a command id of ?1111?. 4.3 exception handling ta b l e 5 9 summarizes the exception conditions detected by the device and the response for each exception. table 59. exception handling condition description s st u response exception self-test request power on reset n/a power applied clear command 1 1 0 ? reference section 3.6 v reg under-voltage n/a v reg < v porcreg_f ? device held in reset. ? no response to dsi commands. ? device must be re-initialized when v reg returns above v porcreg_r v rega under-voltage n/a v rega < v porcreg_f ? device held in reset. ? no response to dsi commands. ? device must be re-initialized when v rega returns above v porcrega_r v hcap under-voltage transient disabled v hcap < v porcreg_f for less than t hcap_por , st disabled 001 ? dsi read acceleration data short response = zero. ? dsi read acceleration data long response = normal. ? device does not need to be re-initialized if v hcap returns above v porhcap_r before t hcap_por enabled v hcap < v porcreg_f for less than t hcap_por , st enabled 011 ? dsi read acceleration data short response = self-test data. ? dsi read acceleration data long response = self-test data. ? device does not need to be re-initialized if v hcap returns above v porhcap_r before t hcap_por v hcap under-voltage n/a v hcap < v porcreg_f for longer than t hcap_por ? device is reset and will continue to reset every t hcap_por until vhcap returns above v porhcap_r , or an internal supply under-voltage condition occurs. ? no response to dsi commands. ? device must be re-initialized when v hcap returns above v porhcap_r capacitor test failure n/a ? device is reset and will continue to be reset every t por_captest until the capacitor failure is removed. ? no response to dsi commands. ? device must be re-initialized when capacitor failure is removed. dsi frame timeout n/a v busin < v thf for longer than t to ? device is reset and will continue to be reset every t to until the busin voltage returns above v thf or a supply under-voltage condition occurs. ? no response to dsi commands. ? device must be re-initialized when v busin returns above v thf fuse crc fault (factory array) disabled crc failure detected in factory programmed otp array and the lock_f bit is set. st disabled 100 ? dsi read acceleration data short response = zero. ? dsi read acceleration data long response = normal. enabled crc failure detected in factory programmed otp array and the lock_f bit is set. st enabled 110 ? dsi read acceleration data short response = zero. ? dsi read acceleration data long response = self-test data. fuse crc fault (user array) disabled crc failure detected in user pro- grammed otp array and the lock_u bit is set. st disabled 100 ? dsi read acceleration data short response = zero. ? dsi read acceleration data long response = normal. enabled crc failure detected in user pro- grammed otp array and the lock_u bit is set. st enabled 110 ? dsi read acceleration data short response = zero. ? dsi read acceleration data long response = self-test data. temperature out of range disabled temperature out of range, st disabled. 100 ? dsi read acceleration data short response = zero. ? dsi read acceleration data long response = normal. enabled temperature out of range, st enabled. 110 ? dsi read acceleration data short response = zero. ? dsi read acceleration data long response = self-test data. self-test enabled enabled st enabled 1 1 0 ? internal self-test circuitry enabled. ? dsi read acceleration data short response = self-test data. ? dsi read acceleration data long response = self-test data. self-test lockout disabled 2 consecutive disable self-test dsi commands received. 000 ? internal self-test circuitry disabled. ? enable self-test dsi command does not enable self-test. normal response to enable self-test dsi comma nd except the st bit is not set. ? dsi clear command or reset disables lockout.
sensors freescale semiconductor, inc. 43 mma26xxnkw 5 package 5.1 case outline drawing reference freescale case outline drawing # 98asa00090d http://www.freescale.com/files/shared /doc/package_info/98asa00090d.pdf 5.2 recommended footprint reference freescale application note an3111, latest revision: http://www.freescale.com/files /sensors/doc/app _note/an3111.pdf table 60. revision history revision number revision date description of changes 4 03/2012 ? added safeassure logo, changed first paragraph and disclaimer to include trademark information.
mma26xxnkw rev. 4 03/2012 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale and the freescale logo are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. safeassure and xtrinsic are trademarks of freescalesemiconductor, inc. all other product or service names are the property of their respective owners. ? 2012 freescale semiconductor, inc. all rights reserved. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor lite rature distribution center 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http:/www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp.

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